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devices incorporated video imaging products 1 lf3310 horizontal / vertical digital image filter 11/08/2001-lds.3310-h q q q q q 83 mhz data rate q q q q q 12-bit data and coefficients q q q q q on-board memory for 256 horizontal and vertical coefficient sets q q q q q lf interface tm allows all 512 coefficient sets to be updated within vertical blanking q q q q q selectable 12-bit data output with user-defined rounding and limiting q q q q q seven 3k x 12-bit, programmable two-mode line buffers q q q q q 16 horizontal filter taps q q q q q 8 vertical filter taps q q q q q two operating modes: dimension- ally separate and orthogonal q q q q q supports interleaved data streams q q q q q horizontal filter supports decima- tion up to 16:1 for increasing number of filter taps q q q q q 3.3 volt power supply q q q q q 5 volt tolerant i/o q q q q q 144 lead pqfp features description the lf3310 is a two-dimensional digital image filter capable of filtering data at real-time video rates. the device contains both a horizontal and a vertical filter which may be cascaded or used concurrently for two-dimensional filtering. the input, coefficient, and output data are all 12-bits and in twos complement format. the horizontal filter is designed to take advantage of symmetric coefficient sets. when symmetric coefficient sets are used, the horizontal filter can be configured as a 16-tap fir filter. when asymmetric coefficient sets are used, it can be configured as an 8-tap fir filter. the vertical filter is an 8-tap fir filter with all required line buffers contained on-chip. the line buffers can store video lines with lengths from 4 to 3076 pixels. horizontal filter interleave/decima- tion registers (i/d registers) and the vertical filter line buffers allow interleaved data to be fed directly into the device and filtered without separating the data into individual data streams. the horizontal filter can handle a maximum of sixteen data sets interleaved together. the vertical filter can handle interleaved video lines which contain 3076 or less data values. the i/d registers and horizontal accumulator facilitate using decimation to increase the number of filter taps in the horizontal filter. decimation of up to 16:1 is supported. the device has on-chip storage for 256 horizontal coefficient sets and 256 vertical coefficient sets. each filters coefficients are loaded independently of each other allowing one filters coefficients to be updated without affecting the other filters coefficients. in addition, a horizontal or vertical coefficient set can be updated inde- pendently from the other coefficient sets in the same filter. lf3310 b lock d iagram din 11-0 3k line buffer 12 dout 11-0 12 256 coefficient set storage 256 coefficient set storage 16-tap horizontal filter 8-tap vertical filter 3k line buffer 3k line buffer 3k line buffer 3k line buffer 3k line buffer 3k line buffer lf3310 horizontal / vertical digital image filter devices incorporated
devices incorporated lf3310 horizontal / vertical digital image filter 2 video imaging products 11/08/2001-lds.3310-h f igure 1. lf3310 f unctional b lock d iagram din 11-0 3k line buffer dout 11-0 12 32 12 12 12 12 v coef bank 7 v coef bank 6 v coef bank 5 v coef bank 4 12 v coef bank 0 12 v coef bank 1 12 v coef bank 2 12 v coef bank 3 3k line buffer 3k line buffer 3k line buffer 3k line buffer 3k line buffer 3k line buffer 24 24 24 24 24 24 24 24 26 26 12 vca 7-0 vcen 8 12 12 12 12 12 12 12 12 vshen "0" vacc oe alu ab alu ab alu ab alu ab alu ab alu ab alu ab alu ab 13 h coef bank 0 12 h coef bank 1 12 h coef bank 2 12 h coef bank 3 12 13 13 13 13 13 13 13 h coef bank 7 12 h coef bank 6 12 h coef bank 5 12 h coef bank 4 12 25 25 25 25 25 25 25 25 27 27 hca 7-0 hcen 8 "0" hacc data delay hshen clk data delay 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 i eo data reversal 1-16 horizontal lf interface hcf 11-0 hld 12 vertical lf interface vcf 11-0 vld 12 txfr round select limit 12 32 vrsl 3-0 4 hrsl 3-0 4 32 32 configuration and control registers vertical round select limit horizontal i/d registers hpause vpause
devices incorporated video imaging products 3 lf3310 horizontal / vertical digital image filter 11/08/2001-lds.3310-h signal definitions power v cc and gnd +3.3 v power supply. all pins must be connected. clock clk master clock the rising edge of clk strobes all enabled registers . inputs din 11-0 data input din 11-0 is the 12-bit registered data input port. data is latched on the rising edge of clk. hcf 11-0 horizontal coefficient input hcf 11-0 is used to load data into the horizontal coefficient banks and the configuration/control registers. data present on hcf 11-0 is latched into the horizontal lf interface tm on the rising edge of clk when hld is low (see the lf interface tm section for a full discussion). hca 7-0 horizontal coefficient address hca 7-0 determines which row of data in the horizontal coefficient banks is fed to the multipliers in the horizontal filter. hca 7-0 is latched into the horizontal coefficient address register on the rising edge of clk when hcen is low. vcf 11-0 vertical coefficient input vcf 11-0 is used to load data into the vertical coefficient banks and the configuration/control registers. data present on vcf 11-0 is latched into the vertical lf interface tm on the rising edge of clk when vld is low (see the lf interface tm section for a full discussion). vca 7-0 vertical coefficient address vca 7-0 determines which row of data in the vertical coefficient banks is fed to the multipliers in the vertical filter. vca 7-0 is latched into the vertical coefficient address register on the rising edge of clk when vcen is low. outputs dout 11-0 data output dout 11-0 is the 12-bit registered data output port. controls hld horizontal coefficient load when hld is low, data on hcf 11-0 is latched into the horizontal lf interface tm on the rising edge of clk. when hld is high, data can not be latched into the horizontal lf interface tm . when enabling the lf interface tm for data input, a high to low transition of hld is required in order for the input circuitry to func- tion properly. therefore, hld must be set high immediately after power up to ensure proper operation of the input circuitry (see the lf interface tm section for a full discussion). f igure 2. i nput f ormats 11 10 9 2 1 0 C2 11 (sign) 2 10 2 9 2 2 2 1 2 0 11 10 9 2 1 0 C2 0 (sign) 2 C1 2 C2 2 C9 2 C10 2 C11 input data coefficient data f igure 3. h orizontal and v ertical a ccumulator f ormats 31 30 29 2 1 0 C2 20 (sign) 2 19 2 18 2 C9 2 C10 2 C11 31 30 29 2 1 0 C2 20 (sign) 2 19 2 18 2 C9 2 C10 2 C11 horizontal accumulator output vertical accumulator output t able 1. o utput f ormats slct 4-0 s 11 s 10 s 9 s 6 s 5 s 2 s 1 s 0 00000 f 11 f 10 f 9 f 6 f 5 f 2 f 1 f 0 00001 f 12 f 11 f 10 f 7 f 6 f 3 f 2 f 1 00010 f 13 f 12 f 11 f 8 f 7 f 4 f 3 f 2 10010 f 29 f 28 f 27 f 24 f 23 f 20 f 19 f 18 10011 f 30 f 29 f 28 f 25 f 24 f 21 f 20 f 19 10100 f 31 f 30 f 29 f 26 f 25 f 22 f 21 f 20
devices incorporated lf3310 horizontal / vertical digital image filter 4 video imaging products 11/08/2001-lds.3310-h hcen horizontal coefficient address enable when hcen is low, data on hca 7-0 is latched into the horizontal coeffi- cient address register on the rising edge of clk. when hcen is high, data on hca 7-0 is not latched and the registers contents will not be changed. vld vertical coefficient load when vld is low, data on vcf 11-0 is latched into the vertical lf interface tm on the rising edge of clk. when vld is high, data can not be latched into the vertical lf interface tm . when enabling the lf interface tm for data input, a high to low transition of vld is required in order for the input circuitry to func- tion properly. therefore, vld must be set high immediately after power up to ensure proper operation of the input circuitry (see the lf interface tm section for a full discussion). vcen vertical coefficient address enable when vcen is low, data on vca 7-0 is latched into the vertical coefficient address register on the rising edge of clk. when vcen is high, data on vca 7-0 is not latched and the registers contents will not be changed. txfr horizontal filter lifo transfer control txfr is used to change which lifo in the data reversal circuitry sends data to the reverse data path and which lifo receives data from the forward data path. when txfr goes low, the lifo sending data to the reverse data path becomes the lifo receiving data from the forward data path, and the lifo receiving data from the forward data path becomes the lifo sending data to the reverse data path. the device must see a high to low transition of txfr in order to switch lifos. hacc horizontal accumulator control when hacc is high, the horizontal accumulator is enabled for accumula- tion and the accumulator output register is disabled for loading. when hacc is low, no accumulation is performed and the accumulator output register is enabled for loading. hacc is latched on the rising edge of clk. vacc vertical accumulator control when vacc is high, the vertical accumulator is enabled for accumula- tion and the accumulator output register is disabled for loading. when vacc is low, no accumulation is performed and the accumulator output register is enabled for loading. vacc is latched on the rising edge of clk. hshen horizontal shift enable hshen enables or disables the loading of data into the forward and reverse i/d registers in the horizon- tal filter when the device is in dimen- sionally separate mode. if the device is configured such that the horizontal filter feeds the vertical filter, hshen also enables or disables the loading of data into the input register (din 11-0 ). if the device is configured such that the vertical filter feeds the horizontal filter and the vertical limit register is under shift control, hshen also enables or disables the loading of data into the vertical limit register in the vertical round/select/limit circuitry. in orthogonal mode, hshen also enables or disables the loading of data into the input register (din 11-0 ) and the line buffers in the vertical filter. it is important to note that in orthogo- nal mode, either hshen or vshen can disable data loading. both must be active to enable data loading in orthogonal mode. also in orthogo- nal mode, the horizontal and vertical limit registers can not be disabled. when hshen is low, data is loaded into and shifted through the registers hshen controls and the forward and reverse i/d registers on the rising edge of clk. when hshen is high, data is not loaded into or shifted through the registers hshen controls and the i/d registers, and their contents will not be changed. hshen is latched on the rising edge of clk. vshen vertical shift enable vshen enables or disables the loading of data into the line buffers in the vertical filter when the device is in dimensionally separate mode. if the device is configured such that the vertical filter feeds the horizontal filter, vshen also enables or disables the loading of data into the input register (din 11-0 ). if the device is configured such that the horizontal filter feeds the vertical filter and the horizontal limit register is under shift control, vshen also enables or disables the loading of data into the horizontal limit register in the hori- zontal round/select/limit circuitry. in orthogonal mode, vshen also enables or disables the loading of data into the input register (din 11-0 ) and the forward and reverse i/d registers in the horizontal filter. it is important to note that in orthogonal mode, either hshen or vshen can disable data loading. both must be active to enable data loading in orthogonal mode. also in orthogonal mode, the horizontal and vertical limit registers can not be disabled. when vshen is low, data is loaded into and shifted through the registers vshen controls and the line buffers on the rising edge of clk. when vshen is high, data is not loaded into or shifted through the registers vshen controls and the line buffers, and their contents will not be changed. vshen is latched on the rising edge of clk.
devices incorporated video imaging products 5 lf3310 horizontal / vertical digital image filter 11/08/2001-lds.3310-h hrsl 3-0 horizontal round/select/ limit control hrsl 3-0 determines which of the sixteen user-programmable round/ select/limit registers (rsl registers) are used in the horizontal round/ select/limit circuitry (rsl circuitry). a value of 0 on hrsl 3-0 selects rsl register 0. a value of 1 selects round/select/limit register 1 and so on. hrsl 3-0 is latched on the rising edge of clk (see the horizontal round, select, and limit sections for a complete discussion). vrsl 3-0 vertical round/select/limit control vrsl 3-0 determines which of the sixteen user-programmable rsl registers are used in the vertical rsl circuitry. a value of 0 on vrsl 3-0 selects rsl register 0. a value of 1 selects rsl register 1 and so on. vrsl 3-0 is latched on the rising edge of clk (see the vertical round, select, and limit sections for a com- plete discussion). oe output enable when oe is low, dout 11-0 is enabled for output. when oe is high, dout 11-0 is placed in a high-impedance state. hpause lf interface tm pause when hpause is high, the hori- zontal lf interface tm loading sequence is halted until hpause is returned to a low state. this effectively allows the user to load coefficients and control registers at a slower rate than the master clock (see the lf interface tm section for a full discussion). vpause lf interface tm pause when vpause is high, the vertical lf interface tm loading sequence is halted until vpause is returned to a low state. this effectively allows the user to load coefficients and control registers at a slower rate than the master clock (see the lf interface tm section for a full discussion). operational modes dimensionally separate in dimensionally separate mode, the horizontal and vertical filters are cascaded together to form a two-dimensional image filter (see figures 4 and 5). bit 1 in configura- tion register 4 determines the cascade order. if this bit is set to 0, data on din 11-0 is fed into the horizontal filter first. the horizontal filter then feeds data into the vertical filter. if this bit is set to 1, data on din 11-0 is fed into the vertical filter first. the vertical filter then feeds data into the horizontal filter. orthogonal in orthogonal mode, the horizontal and vertical filters are used concur- rently to implement an orthogonal kernel on the input data (see figure 6). din 11-0 horizontal filter vertical filter line buffer 12 12 line buffer line buffer line buffer line buffer line buffer line buffer dout 11-0 12 f igure 4. d imensionally s eparate m ode : h to v din 11-0 horizontal filter vertical filter line buffer 12 line buffer line buffer line buffer line buffer line buffer line buffer dout 11-0 12 12 f igure 5. d imensionally s eparate m ode : v to h
devices incorporated lf3310 horizontal / vertical digital image filter 6 video imaging products 11/08/2001-lds.3310-h the hv filter can handle kernel sizes of 3-3, 5-5, and 7-7 (see figure 7). data delay elements at the input of the horizontal filter and the output of the vertical filter are used to properly align data so that the orthogonal kernel is implemented correctly. the data delays are automatically set to the correct lengths based on the programmed length of the line buffers and the kernel size. kernel sizes of 3-3, 5-5, and 7-7 require that the horizontal filters output be delayed by lb C 2, 2(lb) C 3, and 3(lb) C 4 clock cycles respectively before being added to the vertical filters output (lb is the programmed line buffer length). the data delay at the input of the horizon tal filter handles the lb, 2(lb), and 3(lb) delays. the data delay at the output of the vertical filter handles the C 2, C 3, and C 4 delays. for example, if the line buffers are programmed for a length of 720 and a 5C5 kernel is selected, the horizontal filter input data delay will be 1440 clock cycles and the vertical filter output data delay will be 3 clock cycles. it is important to note that the first 3, 5, or 7 multipliers of the horizontal and vertical filters must be used in orthogonal mode. if other multipli- ers are used, data from the horizontal and vertical filters will not line up correctly because the data delays are calculated assuming that the first 3, 5, or 7 multipliers are used. also, the alus in the horizontal filter should be configured to accept data from the forward i/d register path into alu input a and force alu input b to 0. functional description horizontal filter the horizontal filter is designed to filter a digital image in the horizontal dimension. this fir filter can be configured to have as many as 16-taps when symmetric coefficient sets are used and 8-taps when asymmetric coefficient sets are used. alus the alus double the number of filter taps available, when symmetric coefficient sets are used, by pre-adding data values which are then multiplied by a common coeffi- cient (see figure 8). the alus can perform two operations: a+b and bCa. bit 0 of configuration regis- ter 0 determines the alu operation. a+b is used with even-symmetric coefficient sets. bCa is used with odd-symmetric coefficient sets. also, either the a or b operand may be set to 0. bits 1 and 2 of configuration register 0 control the alu inputs. a+0 or b+0 are used with asymmetric coefficient sets. interleave/decimation registers the interleave/decimation registers (i/d registers) feed the alu inputs. they allow the device to filter up to sixteen data sets interleaved into the same data stream without having to separate the data sets. the i/d registers should be set to a length equal to the number of data sets interleaved together. for example, if two data sets are interleaved together, the i/d registers should be set to a length of two. bits 1 through 4 of configuration register 1 determine f igure 6. o rthogonal m ode din 11-0 horizontal filter vertical filter line buffer 12 line buffer line buffer line buffer line buffer line buffer line buffer dout 11-0 12 data delay data delay f igure 7. 3-3, 5-5, and 7-7 o rthogonal k ernels v 2 v 3 hv 4 h 3 h 5 v 5 v 6 h 2 h 6 h 1 h 7 v 1 v 7 v 1 v 2 hv 3 h 2 h 4 v 4 v 5 h 1 h 5 v 1 hv 2 h 1 h 3 v 3
devices incorporated video imaging products 7 lf3310 horizontal / vertical digital image filter 11/08/2001-lds.3310-h the i/d register length. the i/d registers also facilitate using decimation to increase the number of filter taps. decimation by n is accomplished by reading the horizon- tal filters output once every n clock cycles. the device supports decima- tion up to 16:1. with no decimation, the maximum number of filter taps is sixteen. when decimating by n, the number of filter taps becomes 16n because there are nC1 clock cycles when the horizontal filters output is not being read. the extra clock cycles are used to calculate more filter taps. when decimating, the i/d registers should be set to a length equal to the decimation factor. for example, when performing a 4:1 decimation, the i/d registers should be set to a length of four. when not decimating or when only one data set (non-interleaved data) is fed into the device, the i/d registers should be set to a length of one. hshen enables or disables the loading of data into the forward and reverse i/d registers when the device is in dimensionally separate mode (see the hshen section for a full discussion). when in orthogonal mode, hshen also enables or disables the loading of data into the input register (din 11-0 ) and the line buffers. it is important to note that in orthogonal mode, either hshen or vshen can disable the loading of data into the input register (din 11-0 ), f igure 9. i/d r egister d ata p aths alu ab alu ab coef 7 coef 6 1-16 1-16 1-16 1-16 data reversal alu ab alu ab coef 7 coef 6 1-16 1-16 1-16 1-16 data reversal delay stage nC1 alu ab alu ab coef 6 1-16 1-16 1-16 1-16 data reversal even-tap mode odd-tap mode odd-tap interleave mode 2 coef 7 2 delay stage n f igure 8. s ymmetric c oefficient s et e xamples 1 2 3 4 5 6 7 8 even-tap, even-symmetric coefficient set odd-tap, even-symmetric coefficient set 1 2 3 4 5 6 7 8 even-tap, odd-symmetric coefficient set 1 2 3 4 5 6 7 i/d registers, and line buffers. both must be active to enable data loading in orthogonal mode. i/d register data path control the multiplexer in the middle of the i/d register data path controls how data is fed to the reverse data path. the forward data path contains the i/d registers in which data flows from left to right in the block diagram in figure 1. the reverse data path contains the i/d registers in which data flows from right to left. when the filter is configured for an even number of taps, data from the last i/d regis- ter in the forward data path is fed into the first i/d register in the reverse data path (see figure 9).
devices incorporated lf3310 horizontal / vertical digital image filter 8 video imaging products 11/08/2001-lds.3310-h when the filter is configured for an odd number of taps, the data which will appear at the output of the last i/d register in the forward data path on the next clock cycle is fed into the first i/d register in the reverse data path. bit 5 in configuration register 1 configures the filter for an even or odd number of taps. when interleaved data is fed through the device and an even tap filter is desired, the filter should be config- ured for an even number of taps (bit 5 of cr 1 set to 0) and the i/d regis- ter length should match the number of data sets interleaved together. when interleaved data is to be fed through the device and an odd tap filter is desired, the filter should be set to odd-tap interleave mode. bit 0 of configuration register 1 configures the filter for odd-tap interleave mode. when the filter is configured for odd-tap interleave mode, data from the next to last i/d register in the forward data path is fed into the first i/d register in the reverse data path. when the filter is configured for an odd number of taps (interleaved or non-interleaved modes), the filter is structured such that the center data value is aligned simultaneously at the a and b inputs of the last alu in the forward data path. in order to achieve the correct result, the user must divide the coefficient by two. data reversal data reversal circuitry is placed after the multiplexer which routes data from the forward data path to the reverse data path (see figure 10). when decimating, the data stream must be reversed in order for data to be properly aligned at the inputs of the alus. when data reversal is enabled, the circuitry uses a pair of lifos to reverse the order of the data sent to the reverse data path. when txfr goes low, the lifo sending data to the reverse data path becomes the lifo receiving data from the forward data path, and the lifo receiving data from the forward data path becomes the lifo sending data to the reverse data path. the device must see a high to low transition of txfr in order to switch lifos. if decimating by n, txfr should go low once every n clock cycles. when data reversal is disabled, the circuitry functions like an i/d register. when feeding interleaved data through the filter, data reversal should be disabled. bit 6 of configuration register 1 enables or disables data reversal. horizontal rounding the horizontal filter output may be rounded by adding the contents of one of the sixteen horizontal round registers to the horizontal filter output f igure 10. d ata r eversal 1-16 lifo a lifo b txfr f igure 11. h orizontal and v ertical r ound /s elect /l imit c ircuitry rh0 rh15 32 lh0 lh15 24 4 hrsl 3-0 rv0 rv15 32 lv0 lv15 24 4 vrsl 3-0 rnd limit 32 12 rnd limit 32 12 12 12 vertical rsl horizontal rsl data in 32 data in 32 data out data out sh0 sh15 5 sv0 sv15 5 select select
devices incorporated video imaging products 9 lf3310 horizontal / vertical digital image filter 11/08/2001-lds.3310-h (see figure 11). each round register is 32-bits wide and user-programmable. this allows the filters output to be rounded to any precision required. since any 32-bit value may be programmed into the round registers, the device can support complex rounding algorithms as well as standard half-lsb rounding. hrsl 3- 0 determines which of the sixteen horizontal round registers are used in the rounding operation. a value of 0 on hrsl 3-0 selects horizontal round register 0. a value of 1 selects hori- zontal round register 1 and so on. hrsl 3-0 may be changed every clock cycle if desired. this allows the rounding algorithm to be changed every clock cycle. this is useful when filtering interleaved data. if rounding is not desired, a round register should be loaded with 0 and selected as the register used for rounding. round register loading is discussed in the lf interface tm section. horizontal select the word width of the horizontal filter output is 32-bits. however, only 12-bits may be sent to the filter output. the horizontal filter select circuitry determines which 12-bits are passed (see table 1). the horizontal select registers control the horizontal select circuitry. there are sixteen horizontal select registers. each select register is 5-bits wide and user- programmable. hrsl 3-0 determines which of the sixteen horizontal select registers are used in the horizontal select circuitry. a value of 0 on hrsl 3-0 selects horizontal select register 0. a value of 1 selects hori- zontal select register 1 and so on. hrsl 3-0 may be changed every clock cycle if desired. this allows the 12-bit window to be changed every clock cycle. this is useful when filtering interleaved data. select register loading is discussed in the lf interface tm section. horizontal limiting an output limiting function is provided for the output of the horizontal filter. the horizontal limit registers determine the valid range of output values when limiting is enabled (bit 1 in configuration register 5). there are sixteen 24-bit horizontal limit registers. hrsl 3-0 determines which horizontal limit register is used during the limit operation. a value of 0 on hrsl 3-0 selects horizontal limit register 0. a value of 1 selects horizontal limit register 1 and so on. each limit register contains both an upper and lower limit value. if the value fed to the limiting circuitry is less than the lower limit, the lower limit value is passed as the filter output. if the value fed to the limiting circuitry is greater than the upper limit, the upper limit value is passed as the filter output. hrsl 3-0 may be changed every clock cycle if desired. this allows the limit range to be bits function description 0 alu mode 0 : a + b 1: b C a 1 pass a 0 : alu input a = 0 1 : alu input a = forward register path 2 pass b 0 : alu input b = 0 1 : alu input b = reverse register path 11-3 reserved must be set to 0 t able 2. c onfiguration r egister 0 C a ddress 200h bits function description 0 odd-tap interleave mode 0 : odd-tap interleave mode disabled 1 : odd-tap interleave mode enabled 4-1 i/d register length 0000: 1 register 0001: 2 registers 0010: 3 registers 0011: 4 registers 0100: 5 registers 0101: 6 registers 0110: 7 registers 0111: 8 registers 1000: 9 registers 1001: 10 registers 1010: 11 registers 1011: 12 registers 1100: 13 registers 1101: 14 registers 1110: 15 registers 1111: 16 registers 5 horizontal tap number 0 : even number of taps 1 : odd number of taps 6 horizontal data reversal 0 : data reversal enabled 1 : data reversal disabled 11-7 reserved must be set to 0 t able 3. c onfiguration r egister 1 C a ddress 201h
devices incorporated lf3310 horizontal / vertical digital image filter 10 video imaging products 11/08/2001-lds.3310-h changed every clock cycle. this is useful when filtering interleaved data. when loading limit values into the device, the upper limit must be greater than the lower limit. limit register loading is discussed in the lf interface tm section. vertical filter the vertical filter is designed to filter a digital image in the vertical dimen- sion. it is a fir filter which can be configured to have as many as 8-taps. line buffers there are seven on-chip line buffers. the maximum delay length of each line buffer is 3076 cycles and the minimum is 4 cycles. configuration register 2 (cr 2 ) determines the delay length of the line buffers. the line buffer length is equal to the value of cr 2 plus 4. a value of 0 for cr 2 sets the line buffer length to 4. a value of 3072 for cr 2 sets the line buffer length to 3076. any values for cr 2 greater than 3072 are not valid. the line buffers have two modes of operation: delay mode and recirculate mode. bit 0 of configuration register 3 determines which mode the line buffers are in. in delay mode, the data input to the line buffer is delayed by an amount determined by cr 2 . in recirculate mode, the output of the line buffer is routed back to the input of the line buffer allowing the line buffer contents to be read multiple times. bit 1 of configuration register 3 allows the line buffers to be loaded in parallel. when bit 1 is 1, the input register (din 11-0 ) loads all seven line buffers in parallel. this allows all the line buffers to be preloaded with data in the amount of time it normally takes to load a single line buffer. vshen enables or disables the loading of data into the line buffers when the device is in dimensionally separate mode (see the vshen section for a full discussion). when in orthogonal mode, vshen also enables or disables the loading of data into the input register (din 11-0 ) and the forward and reverse i/d registers. it is important to note that in or- thogonal mode, either hshen or vshen can disable the loading of data into the input register (din 11-0 ), i/d registers, and line buffers. both must be active to enable data loading in orthogonal mode. interleaved data the vertical filter is capable of handling interleaved data. the number of data sets it can handle is determined by the number of data values contained in a video line. if the interleaved video line has 3076 data values or less, the vertical filter can handle it no matter how many data sets are interleaved together. bits function description 11-0 line buffer length see line buffer description section t able 4. c onfiguration r egister 2 C a ddress 202h bits function description 0 line buffer mode 0 : delay mode 1 : recirculate mode 1 line buffer load 0 : normal load 1 : parallel load 11-2 reserved must be set to 0 t able 5. c onfiguration r egister 3 C a ddress 203h bits function description 0 hv filter mode 0 : orthogonal mode 1 : dimensionally separate 1 hv direction 0 : horizontal to vertical 1 : vertical to horizontal 3-2 orthogonal kernel size 00 : 3-3 kernel 01 : 5-5 kernel 10 : 7-7 kernel 11 : not used 4 limit register load control 0 : limit registers always enabled 1 : limit registers under shift enable control 11-5 reserved must be set to 0 t able 6. c onfiguration r egister 4 C a ddress 204h bits function description 0 vertical limit enable 0 : vertical limiting disabled 1 : vertical limiting enabled 1 horizontal limit enable 0 : horizontal limiting disabled 1 : horizontal limiting enabled 11-2 reserved must be set to 0 t able 7. c onfiguration r egister 5 C a ddress 205h
devices incorporated video imaging products 11 lf3310 horizontal / vertical digital image filter 11/08/2001-lds.3310-h vertical rounding the vertical filter output may be rounded by adding the contents of one of the sixteen vertical round registers to the vertical filter output (see figure 11). each round register is 32-bits wide and user-programmable. this allows the filters output to be rounded to any precision required. since any 32-bit value may be programmed into the round registers, the device can support complex rounding algorithms as well as standard half-lsb rounding. vrsl 3-0 determines which of the sixteen vertical round registers are used in the rounding operation. a value of 0 on vrsl 3-0 selects vertical round register 0. a value of 1 selects vertical round register 1 and so on. vrsl 3-0 may be changed every clock cycle if desired. this allows the rounding algorithm to be changed every clock cycle. this is useful when filtering interleaved data. if rounding is not desired, a round register should be loaded with 0 and selected as the register used for rounding. round register loading is discussed in the lf interface tm section. vertical select the word width of the vertical filter output is 32-bits. however, only 12-bits may be sent to the filter output. the vertical filter select circuitry determines which 12-bits are passed (see table 1). the vertical select registers control the vertical select circuitry. there are sixteen vertical select registers. each select register address (hex) 0 800 1 801 14 80e 15 80f t able 9. h rz . r ound r egisters register address (hex) 0 c00 1 c01 14 c0e 15 c0f t able 11. h rz . l imit r egisters register address (hex) 0 a00 1 a01 14 a0e 15 a0f t able 12. v rt . r ound r egisters register address (hex) 0 e00 1 e01 14 e0e 15 e0f t able 14. v rt . l imit r egisters register is 5-bits wide and user-programmable. vrsl 3-0 deter- mines which of the sixteen vertical select registers are used in the vertical select circuitry. a value of 0 on vrsl 3-0 selects vertical select register 0. a value of 1 selects vertical select register 1 and so on. vrsl 3-0 may be changed every clock cycle if desired. this allows the 12-bit window to be changed every clock cycle. this is useful when filtering interleaved data. select register loading is discussed in the lf interface tm section. vertical limiting an output limiting function is pro- vided for the output of the vertical filter. the vertical limit registers determine the valid range of output values when limiting is enabled (bit 0 in configuration register 5). there 11 10 9 description 0 0 0 coefficient banks 0 0 1 configuration registers 0 1 0 horizontal select registers 0 1 1 vertical select registers 1 0 0 horizontal round registers 1 0 1 vertical round registers 1 1 0 horizontal limit registers 1 1 1 vertical limit registers t able 8. hcf/vcf 11-9 d ecode are sixteen 24-bit vertical limit registers. vrsl 3-0 determines which vertical limit register is used during the limit operation. a value of 0 on vrsl 3-0 selects vertical limit register 0. a value of 1 selects vertical limit register 1 and so on. each limit register contains both an upper and lower limit value. if the value fed to the limiting circuitry is less than the lower limit, the lower limit value is passed as the filter output. if the value fed to the limiting circuitry is greater than the upper limit, the upper limit value is passed as the filter output. vrsl 3-0 may be changed every clock cycle if desired. this allows the limit range to be changed every clock cycle. this is useful when filtering interleaved data. when loading limit values into the device, the upper limit must be greater than the lower limit. limit register loading is discussed in the lf interface tm section. register address (hex) 0 400 1 401 14 40e 15 40f t able 10. h rz . s elect r egisters register address (hex) 0 600 1 601 14 60e 15 60f t able 13. v rt . s elect r egisters
devices incorporated lf3310 horizontal / vertical digital image filter 12 video imaging products 11/08/2001-lds.3310-h addr 1 coef 0 coef 7 addr 2 coef 0 coef 7 addr 3 coef 0 coef 7 coefficient set 1 coefficient set 2 coefficient set 3 clk hld/vld hcf/vcf 11-0 w1 w1: coefficient set 1 written to coefficient banks during this clock cycle. w2 w3 w2: coefficient set 2 written to coefficient banks during this clock cycle. w3: coefficient set 3 written to coefficient banks during this clock cycle. f igure 12. c oefficient b ank l oading s equence f igure 13. c onfiguration /c ontrol r egister l oading s equence addr 1 data 1 addr 3 data 4 config reg round register limit register clk hld/vld hcf/vcf 11-0 w2 w1: configuration register loaded with new data on this rising clock edge. w3 w4 w2: select register loaded with new data on this rising clock edge. w3: round register loaded with new data on this rising clock edge. data 1 data 3 data 2 addr 4 data 2 data 1 select reg addr 2 data 1 w4: limit register loaded with new data on this rising clock edge. w1 coefficient banks the coefficient banks store the coefficients which feed into the multipliers in the horizontal and vertical filters. there is a separate bank for each multiplier. each bank can hold 256 12-bit coefficients. the banks are loaded using an lf interface tm . there is a separate lf interface tm for the horizontal and vertical banks. coefficient bank loading is discussed in the lf interface tm section. configuration and control registers the configuration registers deter- mine how the hv filter operates. tables 2 through 7 show the formats of the six configuration registers. there are three types of control registers: round, select, and limit. there are sixteen round registers for the horizontal filter and sixteen for the vertical filter. each register is 32-bits wide. hrsl 3-0 and vrsl 3-0 determine which horizontal and vertical round registers respectively are used for rounding. there are sixteen select registers for the horizontal filter and sixteen for the vertical filter. each register is 5-bits wide. hrsl 3-0 and vrsl 3-0 determine which horizontal and vertical select registers respectively are used in the select circuitry. there are sixteen limit registers for the horizontal filter and sixteen for the vertical filter. each register is 24-bits wide and stores both an upper and lower limit value. the lower limit is stored in bits 11-0 and the upper limit is stored in bits 23-12. hrsl 3-0 and vrsl 3-0 determine which horizontal and vertical limit registers respectively are used for limiting when limiting is enabled. configuration and control register loading is discussed in the lf interface tm section. lf interface tm the horizontal and vertical lf interfaces tm are used to load data into the horizontal and vertical coefficient banks respectively. they are also used to load data into the configuration and control registers. the following section describes how the horizontal lf interface tm works. the horizontal and vertical lf interfaces tm are identical in function. if hld and hcf 11-0 are replaced with vld and vcf 11-0 , the following section will describe how the vertical lf interface tm works. hld is used to enable and disable the horizontal lf interface tm . when
devices incorporated video imaging products 13 lf3310 horizontal / vertical digital image filter 11/08/2001-lds.3310-h addr 1 coef 0 coef 1 coefficient set 1 clk hld/vld hcf/vcf 11-0 w1 w1: coefficient set 1 written to coefficient banks during this clock cycle. hpause/vpause coef 7 addr 1 data 1 addr 2 configuration register clk w2 w1: configuration register loaded with new data on this rising clock edge. hpause/vpause data 1 select register w1 w2: select register loaded with new data on this rising clock edge. hld/vld hcf/vcf 11-0 f igure 15. c onfiguration and s elect r egister l oading s equence with hpause and vpause i mplementation f igure 14. c oefficient b ank l oading s equence with hpause and vpause i mplementation hld goes low, the horizontal lf interface tm is enabled for data input. the first value fed into the interface on hcf 11-0 is an address which determines what the interface is going to load. the three most significant bits (hcf 11-9 ) determine if the lf interface tm will load coefficient banks or configuration/control registers (see table 8). the nine least signifi- cant bits (hcf 8-0 ) are the address for whatever is to be loaded (see tables 9-14). for example, to load address 15 of the horizontal coefficient banks, the first data value into the lf interface tm should be 00fh. to load horizontal limit register 10, the first data value should be c0ah. the first address value should be loaded into the interface on the same clock cycle that latches the high to low transition of hld (see figures 12 and 13). the next value(s) loaded into the interface are the data value(s) which will be stored in the bank or register defined by the address value. when loading coefficient banks, the inter- face will expect eight values to be loaded into the device after the address value. the eight values are coefficients 0 through 7. when loading select or configuration registers, the interface will expect one value after the address value. when loading round registers, the interface will expect four values after the address value. when loading limit registers, the interface will expect two values after the address value. figures 12 and 13 show the data loading sequences for the coefficient banks and configuration/control registers. both hpause and vpause allow the user to effectively slow the rate of data loading through the lf interface tm . when hpause is high, the lf interface tm affecting the data used for the horizontal filter is held until hpause is returned to a low. when vpause is high, the lf interface tm affecting the data used for the vertical filter is held until vpause is returned to a low. figures 14 through 17 display the effects of both hpause and vpause while loading coefficient and control data. table 15 shows an example of loading data into the coefficient banks. the following data values are written into address 10 of coefficient banks 0 through 7: 210h, 543h, c76h, 9e3h, 701h, 832h, f20h, 143h. table 16
devices incorporated lf3310 horizontal / vertical digital image filter 14 video imaging products 11/08/2001-lds.3310-h shows an example of loading data into a configuration register. data value 003h is written into configura- tion register 4. table 17 shows an example of loading data into a round register. data value 7683f4a2h is written into horizontal round register 12. table 18 shows an example of loading data into a select register. data value 00fh is loaded into horizontal select register 2. table 19 shows an example of loading data into vertical limit register 7. data value 390h is loaded as the lower limit and 743h is loaded as the upper limit. t able 15. c oefficient b ank l oading f ormat h/vcf 11 h/vcf 10 h/vcf 9 h/vcf 8 h/vcf 7 h/vcf 6 h/vcf 5 h/vcf 4 h/vcf 3 h/vcf 2 h/vcf 1 h/vcf 0 1st word - address 0 0 0000001010 2nd word - bank 0 0 0 1000010000 3rd word - bank 1 0 1 0101000011 4th word - bank 2 1 1 0001110110 5th word - bank 3 1 0 0111100011 6th word - bank 4 0 1 1100000001 7th word - bank 5 1 0 0000110010 8th word - bank 6 1 1 1100100000 9th word - bank 7 0 0 0101000011 f igure 17. l imit r egister l oading s equence with hpause and vpause i mplementation addr 1 data 1 round register clk w1 w1: round register loaded with new data on this rising clock edge. hpause/vpause data 2 data 3 data 4 hld/vld hcf/vcf 11-0 f igure 16. r ound r egister l oading s equence with hpause and vpause i mplementation addr 1 data 1 limit register clk w1 w1: limit register loaded with new data on this rising clock edge. data 2 hld/vld hcf/vcf 11-0 hpause/vpause
devices incorporated video imaging products 15 lf3310 horizontal / vertical digital image filter 11/08/2001-lds.3310-h all four data values are loaded. after the last data value is loaded, the interface will expect a new address value on the next clock cycle. after the next address value is loaded, data loading will begin again as previously discussed. as long as data is loaded into the interface, hld must remain low. after all desired coefficient banks and configuration/control registers are loaded with data, the lf interface tm must be disabled. this is it takes 9s clock cycles to load s coefficient sets into the device. therefore, it takes 2304 clock cycles to load all 256 coefficient sets. assuming an 83 mhz clock rate, all 256 coeffi- cient sets can be updated in 28.8 s, which is well within vertical blanking time. it takes 5s or 3s clock cycles to load s round or limit registers respec- tively. therefore, it takes 256 clock cycles to update all round and limit registers (both horizontal and verti- cal). assuming an 83 mhz clock rate, t able 16. c onfiguration r egister l oading f ormat h/vcf 11 h/vcf 10 h/vcf 9 h/vcf 8 h/vcf 7 h/vcf 6 h/vcf 5 h/vcf 4 h/vcf 3 h/vcf 2 h/vcf 1 h/vcf 0 1st word - address 0 0 1000000100 2nd word - data 0 0 0000000011 t able 17. r ound r egister l oading f ormat h/vcf 11 h/vcf 10 h/vcf 9 h/vcf 8 h/vcf 7 h/vcf 6 h/vcf 5 h/vcf 4 h/vcf 3 h/vcf 2 h/vcf 1 h/vcf 0 1st word - address 1 0 0000001100 2nd word - data r rrr10100010* 3rd word - data r rrr11110100 4th word - data r rrr10000011 5th word - data r rrr0**1110110 r = reserved. must be set to 0. * this bit represents the lsb of the round register. ** this bit represents the msb of the round register. all horizontal and vertical round/ limit registers can be updated in 3.08 s. the coefficient banks and configura- tion/control registers are not loaded with data until all data values for the specified address are loaded into the lf interface tm . in other words, the coefficient banks are not written to until all eight coefficients have been loaded into the lf interface tm . a round register is not written to until
devices incorporated lf3310 horizontal / vertical digital image filter 16 video imaging products 11/08/2001-lds.3310-h done by setting hld high on the clock cycle after the clock cycle which latches the last data value. it is important that the lf interface tm remain disabled when not loading data into it. the horizontal coefficient banks may only be loaded with the horizontal lf interface tm and the vertical coeffi- cient banks may only be loaded with the vertical lf interface tm . the configuration and control registers may be loaded with either the hori- zontal or vertical lf interfaces tm . since both lf interfaces tm operate independently of each other, both lf interfaces tm can load data into their respective coefficient banks at the same time. or, one lf interface tm can load the configuration/control registers while the other loads its respective coefficient banks. if both lf interfaces tm are used to load a configuration or control register at the same time, the vertical lf interface tm will be given priority over the hori- zontal lf interface tm . for example, if the horizontal lf interface tm at- tempts to load data into a configura- tion register at the same time that the vertical lf interface tm attempts to load a horizontal round register, the vertical lf interface tm will be allowed to load the round register while the horizontal lf interface tm will not be allowed to load the configuration register. however, the horizontal lf interface tm will continue to func- tion as if the write occurred. * this bit represents the msb of the lower limit. ** this bit represents the msb of the upper limit. t able 18. s elect r egister l oading f ormat h/vcf 11 h/vcf 10 h/vcf 9 h/vcf 8 h/vcf 7 h/vcf 6 h/vcf 5 h/vcf 4 h/vcf 3 h/vcf 2 h/vcf 1 h/vcf 0 1st word - address 0 1 0000000010 2nd word - data 0 0 0000001111 t able 19. l imit r egister l oading f ormat h/vcf 11 h/vcf 10 h/vcf 9 h/vcf 8 h/vcf 7 h/vcf 6 h/vcf 5 h/vcf 4 h/vcf 3 h/vcf 2 h/vcf 1 h/vcf 0 1st word - address 1 1 1000000111 2nd word - data 0* 0 1110010000 3rd word - data 0** 1 1101000011
devices incorporated video imaging products 17 lf3310 horizontal / vertical digital image filter 11/08/2001-lds.3310-h storage temperature ........................................................................................................... C65c to +150c operating ambient temperature ........................................................................................... C55c to +125c v cc supply voltage with respect to ground ............................................................................ C0.5 v to +4. 5v input signal with respect to ground .......................................................................................... C 0.5 v to 5.5 v signal applied to high impedance output ................................................................................. C0.5 v to 5.5 v output current into low outputs ................................................................................................ ............. 25 ma latchup current ................................................................................................................ ............... > 400 ma esd classification (mil-std-883e method 3015.7) ...................................................................... class 3 m aximum r atings above which useful life may be impaired (notes 1, 2, 3, 8) symbol parameter test condition min typ max unit v oh output high voltage v cc = min., i oh = C4 ma 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 v v ih input high voltage 2.0 5.5 v v il input low voltage (note 3) 0.0 0.8 v i ix input current ground v in v cc (note 12) 10 a i oz output leakage current ground v out v cc (note 12) 10 a i cc1 v cc current, dynamic (notes 5, 6) 250 ma i cc2 v cc current, quiescent (note 7) 2ma c in input capacitance t a = 25c, f = 1 mhz 10 pf c out output capacitance t a = 25c, f = 1 mhz 10 pf e lectrical c haracteristics over operating conditions (note 4) o perating c onditions to meet specified electrical and switching characteristics mode temperature range (ambient) supply voltage active operation, commercial 0 o c to +70 o c 3.00 v v cc 3.60 v active operation, military C55 o c to +125 o c 3.00 v v cc 3.60 v
devices incorporated lf3310 horizontal / vertical digital image filter 18 video imaging products 11/08/2001-lds.3310-h 12345678901234567890123456789 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 12345678901234567890123456789 lf3310C 25 * 18 * 15 12 symbol parameter min max min max min max min max t cyc cycle time 25 18 15 12 t pwl clock pulse width low 10 8 7 5 t pwh clock pulse width high 10 8 7 5 t s0 input setup time 8654 t s1 input setup time (xcen, xrsl)* 8654 t h0 input hold time 1111 t h1 input hold time (xcen, xrsl)* 1.5 1.5 1.5 1.5 t d output delay 13 11 10 8 t dis three-state output disable delay (note 11) 15 13 12 10 t ena three-state output enable delay (note 11) 15 13 12 10 switching characteristics c ommercial o perating r ange (0c to +70c) notes 9, 10 (ns) s witching w aveforms :d ata i/o clk t pwh t pwl t cyc vca 7-0 dout 15-0 123456 t h0 t s0 t d t dis high impedance t ena output n - 1 7 output n hca/vca n hca/vca n+1 hca 7-0 oe controls (except oe) din 11-0 din n+1 din n xcen, xrsl t h1 t s1 * the x represents both horizontal and vertical signals for each case. 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 *d iscontinued s peed g rade
devices incorporated video imaging products 19 lf3310 horizontal / vertical digital image filter 11/08/2001-lds.3310-h 12345678901234567890123456789 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 12345678901234567890123456789 lf3310C 25 * 18 * 15 12 symbol parameter min max min max min max min max t cfs coefficient input setup time 8655 t cfh coefficient input hold time 1 1 1 1.5 t ls load setup time 8654 t lh load hold time 1 1 1 1.5 t ps pause setup time 8654 t ph pause hold time 1.5 1.5 1.5 1.5 c ommercial o perating r ange (0c to +70c) notes 9, 10 (ns) s witching w aveforms : lf i nterface tm clk t pwl t pwh t cyc t ls t cfs t cfh address t lh hcf 11C0 hld 12 45 3 cf 1 cf 0 6 hpause t ps t ph vld vpause vcf 11C0 cf 2 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 *d iscontinued s peed g rade
devices incorporated lf3310 horizontal / vertical digital image filter 20 video imaging products 11/08/2001-lds.3310-h 1. maximum ratings indicate stress specifications only. functional oper- ation of these products at values beyond those indicated in the operating condi- tions table is not implied. exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. the products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. never- theless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. this device provides hard clamping of transient undershoot. input levels below ground will be clamped begin- ning at C0.6 v. the device can with- stand indefinite operation with inputs or outputs in the range of C0.5 v to +5.5 v. device operation will not be adversely affected, however, input cur- rent levels will be well in excess of 100 ma. 4. actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. supply current for a given applica- tion can be accurately approximated by: where n = total number of device outputs c = capacitive load per output v = supply voltage f = clock frequency 6. tested with outputs changing every cycle and no load, at a 40 mhz clock rate. 7. tested with all inputs within 0.1 v of v cc or ground, no load. 8. these parameters are guaranteed but not 100% tested. ncv f 4 2 notes 9. ac specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 v (except t dis test), and input levels of nominally 0 to 3.0 v. output loading may be a resistive divider which provides for specified i oh and i ol at an output voltage of v oh min and v ol max respectively. alternatively, a diode bridge with upper and lower current sources of i oh and i ol respectively, and a balancing voltage of 1.5 v may be used. parasitic capacitance is 30 pf minimum, and may be distributed. this device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. as a result, care must be exercised in the testing of this device. the following measures are recommended: a. a 0.1 f ceramic capacitor should be installed between v cc and ground leads as close to the device under test (dut) as possible. similar capacitors should be installed between device v cc and the tester common, and device ground and tester common. b. ground and v cc supply planes must be brought directly to the dut socket or contactor fingers. c. input voltages on a test fixture should be adjusted to compensate for inductive ground and v cc noise to main- tain required dut input levels relative to the dut ground pin. 10. each parameter is shown as a min- imum or maximum value. input re- quirements are specified from the point of view of the external system driving the chip. setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. responses from the internal circuitry are specified from the point of view of the device. output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. for the t ena test, the transition is measured to the 1.5 v crossing point with datasheet loads. for the t dis test, the transition is measured to the 200mv level from the measured steady-state output voltage with 10ma loads. the balancing volt- age, v th , is set at 3.0 v for z-to-0 and 0-to-z tests, and set at 0 v for z- to-1 and 1-to-z tests. 12. these parameters are only tested at the high temperature extreme, which is the worst case for leakage current. s1 i oh i ol v th c l dut oe 0.2 v t dis t ena 0.2 v 1.5 v 1.5 v 3.0v vth 1 z 0 z z 1 z 0 1.5 v 1.5 v 0v vth v ol * v oh * v ol * v oh * measured v ol with i oh = C10ma and i ol = 10ma measured v oh with i oh = C10ma and i ol = 10ma f igure b. t hreshold l evels f igure a. o utput l oading c ircuit
devices incorporated video imaging products 21 lf3310 horizontal / vertical digital image filter 11/08/2001-lds.3310-h ordering information 0c to +70c c ommercial s creening speed 15 ns 12 ns C55c to +125c mil-std-883 c ompliant C55c to +125c c ommercial s creening 144-pin plastic quad flatpack (q5) LF3310QC15 lf3310qc12 vcc gnd gnd gnd gnd vcc gnd din 11 din 10 din 9 din 8 din 7 din 6 gnd vcc din 5 din 4 din 3 din 2 din 1 din 0 gnd vcc vca 7 vca 6 vca 5 vca 4 vca 3 vca 2 vca 1 vca 0 vcen vshen vcc vcc vcc gnd gnd gnd gnd gnd hcf 11 hcf 10 hcf 9 hcf 8 hcf 7 hcf 6 hcf 5 hcf 4 hcf 3 hcf 2 hcf 1 hcf 0 gnd clk vcc hld gnd vcc hpause gnd vcc hshen gnd vcc txfr vcc gnd gnd vcc vcc vcc gnd gnd hca 7 hca 6 hca 5 hca 4 hca 3 hca 2 hca 1 hca 0 vcc gnd hcen gnd vcc gnd gnd gnd gnd vcf 11 vcf 10 vcf 9 vcf 8 vcf 7 vcf 6 vcf 5 vcf 4 vcf 3 vcf 2 vcf 1 vcf 0 vld vpause vcc vcc vcc gnd vacc gnd vrsl 3 vrsl 2 vrsl 1 vrsl 0 vcc gnd nc nc nc nc dout 11 dout 10 dout 9 dout 8 gnd oe dout 7 dout 6 dout 5 dout 4 dout 3 dout 2 dout 1 dout 0 gnd vcc gnd hrsl 3 hrsl 2 hrsl 1 hrsl 0 hacc gnd 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109

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